The invention relates to a method of forming an interlevel dielectric of the type used in interconnect structures of integrated circuits, and more paticularly to a plasma enhanced chemical vapor deposition method of forming a low-dielectric-constant insulating material.
The designers and makers of large scale integrated circuits continue to make ever-smaller devices which allow for greater speed and increased device packing densities. Sizes of individual features (e.g., the transistor gate length) on ultra-large-scale-integration (ULSI) circuits is shrinking to less than 0.25 microns (.mu.m). The resultant increase in packing densities on a semiconductor chip, and the associated increase in functionality, has greatly increased the number and density of interconnects on each chip.
Smaller on-chip devices, packed closer together, with increased functionality and complexity, require interconnects (lines, vias, etc.) which are smaller, more complex (e.g., more wiring levels), and more closely-spaced. The smaller sizes of the interconnects, which increases resistance, and closer interconnect spacing, leads to RC (resistance-capacitance) coupling problems including propagation delays and cross talk noise between interlevel and intralevel conductors. As interconnect lines, both interlevel and intralevel, become smaller and more closely spaced RC, delays become an increasing part of total signal delays, offsetting any speed advantage derived from smaller device size. RC delays thus limit improvement in device performance. Small conductor size increases the resistivity (R) of metal lines and smaller interline and interlevel spacing increases the capacitance (C) between lines. Use and development of lower-resistivity metals such as copper will continue to reduce the resistivity of interconnect lines. Capacitance can be reduced by employing lower dielectric constant (i.e., lower-k) dielectric materials.
Since capacitance (C) is directly proportional to the dielectric constant (k) of the interconnect dielectric, RC problems presented by ULSI circuits can be reduced if a low-dielectric-constant (low-k) material is used as the insulating material disposed between and around the interlevel and intralevel conductors (the dielectric being referred to herein as the "interconnect dielectric" or "interconnect dielectric material"). What the industry is seeking is a suitable replacement for silicon dioxide (SiO.sub.2), which has long been used as a dielectric in integrated circuits. Silicon dioxide has excellent thermal stability and relatively good dielectric properties, having a dielectric constant of around 4.0. But there is now a need for an interconnect dielectric material which is suitable for use in IC circuit interconnects and which has a lower dielectric constant than SiO.sub.2.
After a long search for possible low dielectric constant materials to be used as an interconnect dielectric in ULSI circuits, the candidates have now been narrowed down to a few, depending upon application. One of the promising materials, which has been actively studied recently and received considerable attention, is fluorinated amorphous carbon (a-F:C).
Fluorocarbon polymers have been studied for more than two decades and most of their applications is for the use of coating materials to protect plastics, fibers, and metals. It is known that a-F:C films can be fabricated using plasma enhanced CVD ("PECVD"). Early experience with a-F:C showed that the films deposited at room temperature could be deposited with a dielectric constant as low as 2.1 and a thermal stability &lt;300.degree. C. Further experimentation showed that if the a-F:C films were deposited at higher substrate temperatures, the thermal stability could be improved up to 400.degree. C., but the dielectric constant increased above .about.2.5.
Table I illustrates how the dielectric constants and thermal stabilities of several members of carbon family compare to a-F:C. It shows that the dielectric constant can be lowered if carbon films contain higher fluorine concentrations. In the PECVD process, the fluorine concentration of a-F:C film depends on the fluorine to carbon ratio in the discharge, which is established by the feed gas composition, RF power input, substrate temperature, and total pressure. The thermal stability is closely related to the degree of crosslinking among the polymer chains. The greater the degree of crosslinking, the more tightly bound the structures are, and the higher the thermal stability. In a PECVD process, either raising substrate temperature, enhancing ion bombardment, or applying low frequency plasma energy can increase the crosslinking in a-F:C films. Higher temperature deposition has the disadvantage of inevitably reducing the fluorine concentration, thereby increasing the dielectric constant.
TABLE I ______________________________________ Relevant properties for several members of carbon family Chemical Thermal Material Composition Structure k Stability ______________________________________ Diamond C Crystalline, fully Greater Very high crosslinked than 5 Hydro- C & H Amorphous 2.7-3.8 350- genated H: 30 at. %- polymer, 400.degree. C. Carbon 50 at. % highly crosslinked (a-H:C) or Diamond- like Carbon (DLC) Fluor- C & F Amorphous 2.1-2.8 300- inated F: 40 at. %- polymer, 420.degree. C. Amor- 50 at. % highly crosslinked phous Carbon (a-F:C) PTFE C & F (--CF.sub.2 --) 2.0 &lt;300.degree. C. or Teflon F: 67 at. % polymer, uncrosslinked ______________________________________
Compared with the processes at low deposition temperatures, the disadvantages of high temperature deposition processes are that it not only increases the dielectric constant, but also leads to poor adhesion to SiO.sub.2 and Si.sub.3 N.sub.4 due to increased thermal stress, and also causes higher leakage current in the films. It appears that a lower deposition temperature is desirable.
Fluorinated amorphous carbon has a dielectric constant k below 3.0 and, depending on the proportion of fluorine (F) in the film, can have a k in the range of 2.0 to 2.5. A major problem with a-F:C is its poor thermal stability. It has heretofore not been possible to prepare a-F:C films with suitable low-dielectric-constant properties (k less than 2.5), and a thermal stability above 400.degree. C. Temperatures in the sintering range (450.degree. C.) typical for manufacturing ULSI chips cause excessive shrinkage of the a-F:C film, probably due to fluorine volatilization. Mechanical strength and adhesion problems also are obstacles to the use of a-F:C as an interconnect dielectric in high-density integrated circuits.
It would be advantageous to have a dielectric material for use in interconnect structures of integrated circuits, alternatively referred to herein as an "interconnect dielectric" which has a low dielectric constant (k=3.0 or less) and improved thermal stability up to 450.degree. C., thus providing a suitable lower-k replacement for silicon dioxide dielectric.
It would also be advantageous to have an a-F:C film which has a dielectric constant of 2.5 or less which is thermally stable to 450.degree. C.
It would also be advantageous to have a method of forming a-F:C film on a silicon substrate using plasma enhanced chemical vapor deposition (PECVD) techniques for depositing low-k a-F:C dielectric material on a semiconductor substrate, wherein the resultant a-F:C is substantially stable up to 450.degree. C.
Accordingly, a plasma enhanced chemical vapor deposition (PECVD) process is provided for depositing a dielectric material on a substrate for use in interconnect structures of integrated circuits. The method comprises steps which include positioning the substrate in a PECVD chamber and heating the substrate to a temperature above 200.degree. C. A flow of fluorine containing gas (FCG) and carbon containing gas (CCG) is introduced into the chamber under sufficient applied energy to form a fluorine and carbon gas plasma in the chamber. The ratio of FCG to CCG is selected to deposit fluorinated amorphous carbon on the substrate. And at the same time as the flow of FCG and CCG is introduced into the chamber, a flow of silane (SiH.sub.4) is introduced into the chamber. The silane increases the thermal stability of the fluorinated amorphous carbon deposited on the substrate.
The preferred fluorine containing gas (FCG) used in the process of the present invention is octafluorocyclobutane (C.sub.4 F.sub.8). The preferred carbon containing gas (CCG) used in the process is methane (CH.sub.4). A suitable ratio of FCG to CCG for the deposit of fluorinated amorphous carbon on the substrate is generally in the range of between 1/1 and 30/1 (FCG/CCG) and, more preferably, generally in the range of 5/1 to 15/1. The percentage of silane gas in the mixture of FCG, CCG, and silane gases introduced into the PECVD chamber is preferably generally in the range of 1% to 15%. The ambient pressure maintained in the PECVD chamber during the introduction of FCG, CCG, and silane into the chamber is preferably generally in the range of 0.3 Torr to 2.0 Torr.
During the introduction of FCG, CCG, and silane into the PECVD chamber, plasma energy, in the form of high frequency (HF) plasma energy, is supplied to ionize the gases introduced into the chamber. Simultaneously, low frequency (LF) energy is introduced into the chamber, to enhance the crosslinking in the deposited a-F:C film. The HF energy has a frequency of 13.56 MHz and is preferably applied at an energy level of between 0.5 Watts and 3.0 Watts per square centimeter of substrate surface. Simultaneously, the LF is supplied in a frequency range generally in the range of 100 KHz to 900 KHz, the low frequency energy level preferably being generally in the range of 0.5 Watts and 3.0 Watts per square centimeter of substrate surface.
The above-described process is carried out for a duration sufficient to deposit a selected thickness of fluorinated amorphous carbon on the substrate. A suitable selected thickness for the a-F:C film deposited using the present invention is generally in the range of 1,000 angstroms to 10,000 angstroms, although the invention is not limited to any specific thickness range. Upon completion of the deposition of a selected thickness of fluorinated amorphous carbon on the substrate, the substrate and deposited fluorinated amorphous carbon is annealed. The present invention allows for annealing at a temperature greater than or equal to 440.degree. C., although the process can be used with anneals of between 300.degree. C. and 550.degree. C. The duration of the anneal is a matter of design choice but will generally exceed 20 minutes and can be 2 hours or more, depending on the design and performance specifications of the integrated circuits being fabricated.